1. Field of Use
The present invention relates to control units and more particularly to a microprogrammable control unit which requires a small number of microinstructions and provides for increased processing efficiency.
2. Prior Art
In general, it is well known that a substantial number of central processing units (CPU's) and input/output processing units (IOP's) employ microprogrammable control units for executing program instructions. A number of such microprogrammable control units include a pair of control stores. The first is a pathfinder control store which is addressed initially by the operation code or a portion for read out of address information. The second control is used for storing microinstructions of a number of microinstruction routines to be referenced by the address information read out from the first control store.
One such system is disclosed in U.S. Pat. No. 4,001,788 which is assigned to the same assignee as named herein. In the patented system, the pathfinder control store when accessed by the operation code of an instruction reads out a word containing at least first and second addresses which are applied in succession to address the second control store for accessing standard and execution microinstruction sequences.
While this arrangement reduces the number of microinstructions required to be stored in the second control store, it still requires microinstructions for interpreting program instruction operation codes during execution of such standard and execution microinstruction sequences. This in turn increases the time period required to interpret and decode program instructions.
In order to reduce the time required for decoding and executing program instructions within a control store or read only memory, one processor utilizes in addition to the typical control storage, a secondary read only memory similar to the control store. The secondary memory is connected through a multiplexer or network to the instruction register to receive a portion of the program instruction to be decoded, the portion and its format being determined by the multiplexer. In addition to addressing the control store, the secondary memory can be used to translate the portion selected from the program instruction so as to form a part of the output microinstruction to be produced in the decoding sequence.
The above arrangement is disclosed in U.S. Pat. No. 3,953,833. While this arrangement reduces the time required to decode program instructions, additional circuits are required for selecting a portion of the instruction to be decoded and its format. Moreover, where the number of possible operations which can be specified by program instructions is large, numbers of unique microinstruction sequences will be required.
Accordingly, it is a primary object of the present invention to provide a microprogrammable control unit which has reduced storage requirements.
It is a further object of the present invention to provide a microprogrammable control unit which provides for increased processing efficiency.